PDP-8/E, PDP-8/M & PDP-8/F Small Computer Handbook

Company:Digital Equipment Corporation
Part:018.00173.2546 S-09-100
Date:1973
Keywords:

Table of Contents

  • Chapter 1 PDP-8/E Story
  • Chapter 2 System Introduction
    • PDP-8/E Basic System
    • KK8-E Central Processing Unit
    • M3800 Major Registers Module
      • Accumulator (AC)
      • Multiplier Quotient Register (MQ)
      • Program Counter (PC)
      • Central Processor Memory Address Register (CPMA)
      • Memory Buffer Register (MB)
      • Data Gates and Adders
    • M8310 Major Registers Control Module
      • Link
      • Major Register Control Circuits
      • Major State Generator
      • Instruction Register (IR)
    • M8320 Bus Loads Module
    • M8330 Timing Generator Module
    • M849 RFI Shield Module
    • KC8-EA Programmers Console
    • M8650 Asynchronous Data Control Module
    • Memory System
      • G227 XY Driver and Current Source Module
      • G619 Planar Stack Board
      • G104 Sense/Inhibit Module
    • Interfacing
    • Differences Between the PDP-8/E and Its Predecessors
    • PDP-8/F and PDP-8/M
  • Chapter 3 System Operation
    • Programmer's Console Operation
    • Memory Organization
    • Memory and Processor Instructions
      • Memory Reference Instructions
      • The Housekeeping Instruction
    • Augmented Instructions
      • The Input/Output Transfer Instruction
      • The Operate Instruction
    • Group 1 Microinstructions
    • Group 2 Microinstructions
    • Group 3 Microinstructions
    • Instruction Execution and Timing
      • Memory Timing
      • FETCH Major State
      • DEFER Major State
      • EXECUTE Major State
  • Chapter 4 Input/Output Operations
    • Programmed Data Transfer
      • Peripheral Device Status
      • Programmed Data Transfer Timing Constraints
    • Program Interrupt Transfers
      • Interrupt System Operation
      • Interrupt System Hardware Components
    • Data Break Transfers
      • Current Address (CA) Register
      • Word Count (WC) Register
      • Data Break Priority
      • Data Break Transfers
      • Single-Cycle Data Break
      • Three-Cycle Data Break
  • Chapter 5 Processor Options
    • Mechanical Expansion Options
    • KE8-E Extended Arithmetic Element
    • Memory Equipment Options
    • Real Time Clock Options
    • KP8-E Power Fail Detect
  • Chapter 6 Internal I/O Options
    • Console Teleprinters
    • CRT Displays
    • X/Y Plotter Options
    • Line Printer Options
    • Data Communications Equipment Options
    • Card Reader Options
    • RK8-E Disk Cartridge System
    • Omnibus Magnetic Tape Options
    • Laboratory Peripherals
    • DB8-E Interprocessor Buffer
  • Chapter 7 External I/O Options
    • External Bus Interface Control Options
    • Random Access Disk Devices
    • Magnetic Tape Options
    • Data Acquisition Peripherals
    • VW01 Writing Tablet
    • FPP-12 Floating Point Processor
    • Data Entry Terminals
    • DW08-A I/O Conversion Panel
  • Chapter 8 Installation Planning and Delivery
    • Pre-Delivery Planning and Site Preparation
      • Processor Options
      • Cabinet Options
      • I/O Cabling Requirements
    • Temperature and Humidity
    • Factors Affecting System Reliability
    • Extended Operation Under Extreme Conditions
    • Electrical Considerations
      • General Power Requirements
      • Power Failure
      • Ground Requirements
    • AC Power Facility Installation and Testing
    • Installation Procedure for PDP-8/M and Teletype
    • Equipment Support Services
      • Maintenance and Service Options
      • Service Agreement
      • Service Contract Coverage
      • Eligibility for Service Contract Coverage
      • Depot Repair
  • Chapter 9 The Omnibus Interfacing
    • Introduction
    • Section 1 Omnibus Description
    • Bus Structure
    • Bus Specifications
    • Systems Configuration
    • Relationship of the External Bus to the Omnibus
    • Omnibus Signals
    • Section 2 How To Choose the Type of I/O Transfer
    • Data Transfer Types
    • Interfacing to the Processor
    • Data Transfer Rates
    • Device Codes
    • Section 3 Designing Basic Programmed I/O Interface Control Circuits
    • Device Selection Circuit
    • Operations Decoder
    • Flag Logic
    • Interrupt Request
    • Output Buffer
    • Input Buffer
    • I/O Control
    • Input/Output Timing for Programmed I/O Interfaces
    • Extended I/O
    • Section 4 Designing a Basic Data Break Interface
    • Break Address
    • Data Paths
    • Status Register
    • Break Priorities
    • Transfer Direction and Loading Logic
    • Data Break Internal Logic and Timing
    • Basic One-Cycle Data Break Interface
    • Timing For Sample Data Break Interface
    • Three-Cycle Data Breaks
    • Design Check List For Single Cycle Data Break Interface
    • Section 5 General Design and Construction Guidelines
    • Interface Design Options
    • Etched Circuit Layout and Construction Rules
    • General Cable Rules and Suggestions
    • DEC Supplied Interface Cables
    • Cabling Rules
    • Interface Timing Criteria
      • General Timing Rules
      • Interrupt Timing
      • Timing Example
      • Timing Requirements For Data Break Facilities
      • Timing and Break Priorities
    • General Propagation Delay Guidelines
      • 2-input NAND Gate Delay
      • Flip-Flop Propagation Delays
      • J-K Flip-Flops
      • One-Shot Delays
    • Maximum Operating Frequency
    • Loading Rules
      • Device Selection Inputs
      • Skip and Interrupt Request Lines
      • Electrical Considerations of Driving a Line
    • Grounding
    • Testing Techniques
      • Initial Checkout
      • System Test
      • Final Testing
    • Programming Rules
    • Design Checklist
    • Section 6 PDP-8/E Interface Hardware
    • W966 & W967 Mounting Boards
    • H851 Edge Connector
    • Module Holders
    • 30-Gauge Insulated Wire
  • Chapter 10 I/O Expansion Techniques
    • Section 1 Positive I/O Bus Interfacing Techniques
    • The Nature of the External Bus
    • External Bus Signals
    • Application
      • Programmed I/O Transfer
      • Program Interrupt Transfers
      • Data Break Transfers
    • Interfacing Techniques
      • PDP-8/I and 8L-Type Peripherals
      • Customer Peripherals
      • DEC Logic Module Interfacing
      • Customer Designed Interfaces
      • Restrictions and Criteria
        • Cooling
        • Signal Terminating
        • Timing Criteria
    • Cabling Rules and Suggestions
    • Section 2 Omnibus Interfacing Using "Off the Shelf" Modules
    • Omnibus Signal Summary
    • The Building Block Approach
    • M783 Bus Drivers
    • M784 Bus Receivers
    • M785 Bus Transceiver
    • M9190 M935 Kit
    • H803 Connector Block
    • M935 Bus Connector
    • H9190 Mounting Panel
    • H019 Mounting Bar
    • Interface Example Paper Tape Reader
    • Input/Output Transfer (IOT) Instruction Usage
    • System Operation
    • M-Series Module Summary
    • K-Series Module Summary

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