The interface between controller and drive is limited to the selection of 4 heads maximum (only 2 head-select lines).
The controller must change the state of the Reduced Write Current signal to the ST-506 (on pin 2 of the control cable) depending on the cylinder in use: signal false for cylinders 0 to 127, signal true for cylinders 128 to 152.
Step pulses to the drive must not be sent be the controller at a rate faster than 1 pulse per 3 milliseconds. The ST-506 physically steps the heads on receipt of each step pulse.
Release of the ST-412 Drive
Reference 3 indicates that the interface between controller and drive remains the same, and therefore the limitation of 4 heads maximum remains.
The ST-412 does not use the Reduced Write Current signal from the controller. The controller/drive interface still maintains that signal though (for possible use by other drives no doubt).
Buffered seek introduced for improved performance: step pulses can be issued at a rate faster than what the ST-412 can physically step the heads. See page 18 of reference 3 for a reason as to why there is an increase in performance.
It is very important to note that the ST-412 cannot accept the step pulses at any rate. Reference 3 includes, "Any pulses issued at a rate between 200 µs and 3 msec may be lost". This general rule applies to other drives as well. For examples, see the table at the bottom of this link. Therefore, when matching a drive to a controller, you must ensure that the controller is issuing step pulses at rate that falls within the drive's specification.
Hardware Change #1 to Interface
At the time of introduction of the ST-506 and the later ST-412, the signal on pin 4 of the control cable was designated as "RESERVED (HEAD SELECT 2 IN FUTURE PRODUCTS)".
At some point, the pin 4 signal did in fact become "HEAD SELECT 2". Together with pins 14 and 18, it allowed drives with up to 8 heads to be used.
And so if you have a drive with between 5 and 8 heads, you need a controller that generates the "HEAD SELECT 2" signal on pin 4.
This change must have occured quite early. Reference 5 contains the circuit diagram of the first controller (made for IBM by Xebec) used in the IBM XT. That is circa 1983, and the diagram shows that pin 4 is generating the "HEAD SELECT 2" signal.
Hardware Change #2 to Interface
In the original specification, the signal on pin 2 of the control cable is designated as "REDUCED WRITE CURRENT". Only very early drives would have required a 'reduced write current' signal.
The Xebec controller (circa 1983) referred to in the previous section has pin 2 as "REDUCED WRITE CURRENT".
At some point, the signal on pin 2 started to be used as "HEAD SELECT 3" so that drives with up to 16 heads could be used.
IBM released the first AT in 1984, and reference 5 contains details of its controller (made for IBM by Western Digital). The description includes "with up to 16 read/write heads" and the circuit diagram has pin 2 labelled as "HS3-/RWC- ".
Reference 3, dated 1985, contains the connector pinout for another Western Digital controller, and that has pin 2 labelled as "RWC/HS3".
Some controllers have a jumper/switch that allows you to change the function of pin 2 between "REDUCED WRITE CURRENT" and "HEAD SELECT 3". The Western Digital WD1003A- RA2 is an example.
And so if you have a drive with between 9 and 16 heads, you need a controller that generates the "HEAD SELECT 3" signal on pin 2.